Bus switches are useful for a variety of applications such as telecommunications, personal computer (PC), networking, and graphics. The basic, simple structure of a transistor bus switch is ideal for higher speed applications. Bus switches may have many transistors in parallel that are packaged together in a single integrated circuit (IC) chip package, allowing for parallel signals on a bus to be switched together.
FIG. 1 shows a prior-art bus switch. Bus switch chip 10 multiplexes an A bus and a B bus, that are connected on the left, to a C bus connected on the right. A control or select signal CSEL is input to bus switch chip 10 and is buffered by non-inverting buffer 16 to generate ASEL and inverter 18 to generate BSEL. When ASEL is high, BSEL is low, and bus-switch transistors 12 are turned on and bus-switch transistors 14 are turned off. A-bus signals C0+A, C0−A, C1+A, C1−A, C2+A, C2−A, C3+A, C3−A, applied to the drains of bus-switch transistors 12 are connected to C-bus signals C0+, C0−, C1+, C1−, C2+, C2−, C3+, C3− that are connected to the sources of bus-switch transistors 12. A total of four logical signals are switched, as each logical signal is carried on differential signals designated +, −.
When ASEL is low, BSEL is high, and bus-switch transistors 12 are turned off and bus-switch transistors 14 are turned on. B-bus signals C0+B, C0−B, C1+B, C1−B, C2+B, C2−B, C3+B, C3−B, applied to the drains of bus-switch transistors 14 are connected to C-bus signals C0+, C0−, C1+, C1−, C2+, C2−, C3+, C3− that are connected to the sources of bus-switch transistors 14.
Higher-speed applications can benefit from differential signaling. To signal a logical high, the + signal goes high while the − signal goes low. When the + signal goes low and the − signal goes high, a logical low is signaled. Since the difference in the +, − signal lines is detected, only a small voltage difference is needed to overcome noise that is common to both +, − signal lines. Thus differential signaling often used reduced voltage swings or small signals. For example, when a 3.3-volt power supply is used, differential signals may switch from 2.7 volts to 3.3 volts. The voltage swing is limited to 0.6 volts, rather than the full 3.3 volts. This reduced voltage swing reduces the amount of charge that must be moved to charge and discharge capacitances, reducing the switching delays.
Several standards for differential signaling with small signals are known. Transmission-minimized differential signaling (TMDS) is one such standard that is used for video applications such as Digital Visual Interface (DVI) and High-Definition Multimedia Interface (HDMI). TMDS limits voltage swings to 2.7-3.3 volts.
FIGS. 2A-B show reduced-voltage-swing communication using a TMDS transmitter and receiver. In FIG. 2A, TMDS transmitter 30 uses switches 32 to switch current from current source 34 between the two complementary differential signal lines of differential lines 28. TMDS receiver 20 has comparator 22 that compares the voltages on differential lines 28 to determine the state of logical data D that was transmitted from TMDS transmitter 30. Pullup resistors 24 to a 3.3-volt Vcc power supply bias differential lines 28.
Differential lines 28 may be carried through cable 26 between TMDS transmitter 30 and TMDS receiver 20. Cable 26 may contain one or more ground wires or sheaths that connect the grounds in TMDS transmitter 30 and TMDS receiver 20. When TMDS transmitter 30 and TMDS receiver 20 operate using a Vcc power supply of 3.3 volts or above, the voltage swing on differential lines 28 can be limited to the range of 2.7 to 3.3 volts, as shown in FIG. 2B.
Higher data rates have required the use of better process technologies for bus switch chip 10. As the physical sizes of bus-switch transistors 12, 14 are shrunk, breakdown voltages also decrease. Thus the voltages applied to bus-switch transistors 12, 14 must be scaled downward as speeds increase. Power-supply voltages of 5 volts have been reduced to 3.3 volts and now to 2.0 or 1.8 volts. Very high-speed applications such as for 1.65 Giga bits per second (Gbps) benefit from the lower capacitances of transistors made with advanced process technologies that typically use 2.0-volt and below power supply voltages.
Although the gate voltages may sometimes be increased above the power supply voltage using a charge pump, the source and drain voltages on bus-switch transistors 12, 14 should remain below the power-supply voltage, or no more than 0.3 volt above the power-supply voltage or 0.3 volt below ground to prevent damage or latch up.
Differential signaling standards such as TMDS were designed for higher power-supply voltages such as 3.3 volts and above. Since the voltage swing of 2.7-3.3 volts is greater than a 2.0-volt power supply, operating bus switch chip 10 with a 2.0-volt power supply would not allow TMDS signals to pass through, as voltages above the 2.0-volt power supply would be clipped. Thus simply using a 2.0-volt Vcc with bus switch chip 10 does not appear to be useful for switching TMDS signals that operates at 2.7-3.3 volts. However, bus switch chip 10 designed for 3.3-volt power supplies may have too much capacitance due to the larger transistor sizes needed to protect against breakdown and damage from the higher voltages.
Newer differential signaling standards have reduced ranges of voltage swings. These newer standards such as low-voltage differential signaling (LVDS) are useful with reduced power supplies, since the differential voltage swing is well below the power supply voltage. Unfortunately, some standards do not use LVDS, but instead use TMDS, perhaps to allow use with legacy devices such as older DVD and video cards. These TMDS applications are still important, even though the TMDS voltage swings are designed for use with higher power supply voltages that were used with legacy video cards.
What is desired is to use a low-capacitance bus switch chip designed for 2.0-volt power supplies for switching TMDS signals that have voltage swings from 2.7-3.3 volts.